In the dynamic realm of optical networking, the landscape constantly evolves with the introduction of groundbreaking technologies. A pivotal stride in this progression is marked by the arrival of 400G SR4 transceivers, not only broadening short-reach options but also laying a foundation for the upcoming shift to 800G. In this post, we will delve into the intricacies of these transceivers, exploring their impact on network infrastructure and their role in shaping the future of data transmission.
The first wave of 400G transceivers were built on a foundation of 8x56G PAM4 of the original QSFP-DD and OSFP MSA. Short-reach transceivers emerged from these MSAs with not only eight lanes at the host, but eight optical lanes, exemplified by the popular 400G SR8 and the innovative 400G SR4.2 "bidi" transceiver. The 50G VCSELs used in the optical side lacked the scalability necessary for a roadmap to 800G. The progress in 100G VCSEL technology, coupled with the demands of artificial intelligence (AI) and machine learning (ML) clusters, led to the development of the 400G SR4.
The 400G SR4 follows a common optical interface across all form factor technologies. However, these form factors differ significantly in how they interface with the host and the network.
Enter the OSFP-RHS SR4, known as the 'Flat top,' designed for network adapters in AI and ML clusters, seamlessly integrating with graphics processing units (GPU) structures. Differentiating itself from legacy OSFP form factor, the OSFP-RHS eliminates the heat sink from the transceiver shell and adopts a 4x112G configuration on the host, diverging from the original 8x50G. It seamlessly interfaces directly with the leaf level of the networking cluster, aligning with the demands of advanced computing environments.
The OSFP112 form factor, often referred to as the 'Finned' transceiver, adheres to the type 2 physical specification of the OSFP MSA. Its defining feature lies in the heat sink, which may be open to expose its fins or closed with a smooth top. A critical departure from legacy OSFP transceivers is the adoption of a 4x112G configuration on the host, steering clear of the traditional 8x50G paradigm. Deployed primarily in the switching levels of AI and ML clusters, its design aligns with the need for efficiency and adaptability, supporting specialized 2x200G or 2x100G ‘breakouts’ in these advanced computing environments.
Moving on to the QSFP112, the QSFP version of a 112G SerDes on the host transceiver. Initially utilized in 400G network adapters and eventually in network switches, QSFP112 network ports exhibit backward compatibility with QSFP56 and QSFP28 transceivers.
Casting the spotlight on QSFP-DD, specifically the QSFP56-DD "QSFP-DD" SR4, it distinguishes itself by offering 400G SR4 compatibility with 56G SerDes QSFP-DD switches. Similar to the legacy 400G DR4 interface, this transceiver incorporates a digital signal processor (DSP) and gearbox to seamlessly retime between four optical lanes and eight lanes at the host, ensuring optimal performance in diverse networking environments.
A crucial note to users of all 400G SR4 transceivers is the movement towards a lower back reflectance optical connector, the MPO-12/APC.
As we meticulously scrutinize the intricacies of these technological advancements, it becomes evident that the future of data transmission is being meticulously shaped by these innovative transceiver technologies, promising heightened efficiency and adaptability in the ever-evolving landscape of optical networking.